Cadence Design Systems Software
Welcome to the home page of the Cadence Users Group at Cooper Union for the Advancment of Science and Art. This page contains information about the Cadence design tools used extensively in our analog and digital integrated circuit engineering classes. Students enrolled in the Electronic Systems and Materials track are required to take the Integrated Circuit Engineering (ECE341) class in the Spring Semester of their junior year. Each pair of students submits one or more circuits to a foundry for fabrication under the auspices of the MOSIS organization.
With funding from the Keck Foundation, an Integrated Circuit Engineering laboratory was established in 1994 with state-of-the-art computer-aided design (CAD) tools, computer platforms and their peripherals for the design of VLSI (Very Large Scale Integration) circuits. Integrated circuits, comprising from 20 to 20,000 transistors are designed from the bottom up using industry standard layout and simulation tools. Cadence Design Systems make their tools available at a massive discount through their educational program. In 1998, the first steps were taken to replace the original hardware. A new server, a SUN UltraSparc II purchased by Cooper Union, was equipped with a RAID storage system to provide a significant decrease in the access time, combined with an increase in the level of data and program security. The speed of the network was upgraded from 10 Mbits/sec to 100 Mbits/sec and the original computers were replaced with fourteen Sun Ultra 10 workstations. This has reduced considerably the time required to process circuits through the different design stages.
Integrated circuit fabrication commences with a schematic drawing of the circuit using Cadence's Composer schematic editor. The schematic is then converted into a netlist for input to the Analog Design Environment circuit simulator to verify that its performance meets the required specifications. The behavior of the transistors is derived from parameters supplied by the silicon foundry.
The simulated schematic circuit is then laid out as a planar array of transistors using Cadence's Virtuoso Layout editor. A further netlist is extracted from the layout and resimulated with the passive parasitic components associated with the transistor interconnections. After verification, the layout is sent to the foundry for fabrication.
The Integrated Circuit Design Experience
Students, working in pairs to comply with MOSIS funding regulations, undertake four design exercises using MOS transistors. The first two exercises move the student, from transistors in schematic form, to the transistor as a planar device with a specific geometric pattern. The exercises comprise five circuits with increasing complexity. Simple inverting amplifiers, with a diode connected transistor as the load, are followed by inverting amplifiers with active current sources as the load. Specifications are limited to gain, slew rate, supply voltage and fabrication technology. Students use supplied small signal models to set the sizes of the transistors. After layout, the circuit is extracted and re-simulated with close attention to the upper 3dB frequency and the influence of parasitic capacitance. The circuit with the active current source load presents more of a challenge because the design of the biasing circuit is very much in the hands of the student. The principal outcome of this assignment is to gain familiarity with the layout and simulation software, and to reach the conclusion that the software is merely a tool used by the circuit designer.
The final part of the preliminary design exercises is a simple operational transconductance amplifier. The circuit is supplied with specifications still limited to overall gain and slew rate, with guidelines for quiescent current and goals for the CMRR, PSRR and frequency response. This exercise rapidly introduces the student to the concept and reality of compromise in integrated circuit engineering. The open-ended nature of the exercise usually presents a significant challenge to most students. During its execution, they gain confidence in design and start to learn the art of compromise.
Design exercise three is presented as a set of specifications for a complete operational amplifier with internal frequency compensation. Values for the open loop gain, unity gain frequency and phase margin must be met by the circuit; other parameters such as the CMRR, output voltage swing and common mode input range must satisfy minimum requirements but improvements are strongly encouraged. This exercise introduces a variety of scenarios into the design experience. Students start to appreciate that numerical simulation packages such as HSpice and Spectre often require intelligent intervention to achieve satisfactory convergence. The need to meet specifications, which often appear to be mutually exclusive, encourages the student to adopt a methodical approach to design. Within this exercise, there is a great deal is of latitude in the design process. The architecture of the amplifier is chosen by the student as is the structure of the layout. It is emphasized that the greater the effort expended in this assignment, the easier the final project will be. The outcome of the second exercise is a thorough grounding in the principles of integrated circuit engineering. The reward of a working amplifier, complete with layout, provides compensation for a tough exercise.
The final project is a MAD (mixed analog and digital) circuit. Currently, this is a phase-locked loop with a center frequency of 100 MHz. Previous circuits have included a four-bit flash ADC, implemented with between 400 and 500 MOS transistors; a three-bit ADC with an on board bandgap voltage reference. The ADC specifications include the input voltage range, sensitivity and the operating conditions. The overall goal remaining is to design the device to operate as fast as possible at 100°C. The first task of each group is to design a comparator within which positive feedback is used to achieve the highest gain with minimum propagation delay. Since this is to be used as a standard cell, great attention must be paid to layout both from the perspective of interconnection and isolation of analog and digital signals. The final part of the design is a thermometer decoder for the output of the comparator stack. This introduces students to CMOS digital circuits.
The ADC is a considerable project for junior EE students. We feel however that the difficulty of the exercise is a very valuable design experience for the reasons mentioned.
Integrated Circuit Engineering (ECE341)
Students entering this class are equipped with an understanding of the fundamental building blocks of analog integrated circuits and a thorough comprehension of frequency response and feedback. Focussing on analog design, the assignments for this class comprise a series of design exercises in which circuits are designed and laid out from the transistor level up. The first major circuit is an operational amplifier, chosen to bring together feedback, frequency response and blocks of transistors as circuit components. The other major exercise is a self-contained, four bit, flash analog to digital converter.
Integrated circuit fabrication and technology. Device modeling, thermal effects. VLSI CAD design tools. Circuit layout, extraction and simulation. Design and analysis of multistage MOS operational amplifiers, OTA architectures. Nonlinear circuits, comparators. Analog switches. Sample and hold circuits. Bandgap reference circuits. MOS digital circuit design and layout, hierarchical approaches. Final design project is a mixed analog/digital circuit, e.g., flash A/D converter.
Digital Integrated Circuit Engineering (ECE441)
Design of CMOS combinational logic gates, layout and simulation. Standard cell construction. State machines. Complex gate design- AOI, XOR, flip-flops. Sequential logic systems, clocks. Design of arithmetic building blocks, multipliers, memory, FPGAs. System design and HDLs. Floor-planning. System architecture. Term project to design and fabricate of an ASIC using a variety of VLSI CAD tools.