The Cooper Union Albert Nerken School of Engineering has recently executed a three-way non-disclosure agreement with Taiwan Semiconductor Manufacturing Company (TSMC) and MUSE Semiconductor LLC on the use of TSMC’s Complementary Metal-Oxide Semiconductor (CMOS) 65nm Radio Frequency Mixed-Signal General Purpose process. The agreement was spearheaded by Ja-beom Koo, assistant professor of electrical engineering, and will include TSMC’s Process Design Kit (PDK) libraries for both Analog/Radio Frequency and Digital components.

TSMC is the world’s largest contract manufacturer of semiconductor chips, otherwise known as integrated circuits, that power our phones, laptops, cars, watches, refrigerators, and more. TSMC accounts for more that 53% of the global semiconductor foundry market. Their client list includes Apple, Intel, Qualcomm, AMD, and Nvidia. MUSE Semiconductor LLC provides Multi Project Wafer (MPW) services to university researchers, like Cooper Union. 

CMOS 65nm technology is one of the main-stream technologies widely used through many high-tech companies in the world. The production linewidth for the integrated circuit will be 65nm (65x10-9) meters. This is roughly three orders of magnitude smaller than a strand of human hair. It is a complementary metal-oxide-semiconductor which refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits. This process line mainly fits for low power analog and wireless chip design. In addition, all digital component assets for the digital circuit design will be provided in this agreement. 

At Cooper, this technology will be utilized through TSMC’s PDK library in various levels of circuit related curriculums, from fundamental courses for sophomores to senior elective courses and projects. Students will be able to learn the basics of semiconductor devices to the advanced design techniques at the senior level. The goal would be for students to ship their design to TSMC via MUSE and receive their own chips for testing. Having hands-on experience in all stages of chip design, from the design phase up to testing real chips, at the undergraduate level is very rare and will be an invaluable asset for students to have going forward.